1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a BGA (Ball Grid Array) package with interdigitated power ring and ground ring.
2. Description of Related Art
BGA (Ball Grid Array) is an advanced type of semiconductor packaging technology which is characterized in the use of a substrate whose front side is mounted with a semiconductor chip and whose back side is mounted with a grid array of solder balls. During SMT (Surface Mount Technology) process, the BGA package can be mechanically bonded and electrically coupled to an external printed circuit board (PCB) by means of these solder balls.
Typically, the BGA substrate is formed with a power ring and a ground ring on the front side thereof The power ring is a ring-shaped electrically-conductive trace surrounding the packaged chip and is used to deliver the power from the external PCB to the packaged chip during operation, and the ground ring is a ring-shaped electrically-conductive trace arranged alongside the power ring and is used to connect the ground pads of the packaged chip to grounding lines on the external PCB.
FIGS. 1A-1B show a typical BGA package with power ring and ground ring (note that FIGS. 1A-1B are simplified schematic diagrams showing only a small number of components; the actual BGA structure and circuit layout may be much more complex).
As shown, this BGA package includes: (a) a substrate 100 having A front side 100a and a back side 100b; (b) a ground ring 110 formed on the front side 100a of the substrate 100; (c) a power ring 120 formed alongside the ground ring 110; (d) a plurality of I/O pads 130 formed over the front side 100a of the substrate 100; (d) a plurality of vias (electrically-conductive through-holes) 141, 142, 143 penetrating the substrate 100, which include a subgroup of ground vias 141 each having an upper end connected to the ground ring 110 and a bottom end exposed on the back side 100b of the substrate 100; a subgroup of power vias 142 each having an upper end connected to the power ring 120 and a bottom end exposed on the back side 100b of the substrate 100; a subgroup of I/O vias 143 each having an upper end connected to one of the I/O pads 130 and a bottom end exposed on the back side 100b of the substrate 100; (e) a solder mask 150 formed over the front side 100a of the substrate 100 while exposing the ground ring 110, the power ring 120, and the I/O pads 130; (f) a semiconductor chip 160 having ground pads 161, power pads 162, and I/O pads 163, and which is mounted on the front side 100a of the substrate 100 within the area surrounded by the ground ring 110 and the power ring 120; (g) a set of bonding wires 170, including a subset of ground wires 171 for connecting the chip""s ground pads 161 to the ground ring 110; a subset of power wires 172 for connecting the chip""s power pads 162 to the power ring 120; and a subset of I/O wires 173 for connecting the chip""s I/O pads 163 to the substrate""s I/O pads 130; and (h) a ball grid array (an array of solder balls) 180 provided on the back side 100b of the substrate 100, which includes a subgroup of ground balls 181 bonded to the ground vias 141; a subgroup of power balls 182 bonded to the power vias 142; and a subgroup of I/O balls 183 bonded to the I/O vias 143. When this BGA package is mounted on an external PCB (not shown), it allows the ground balls 181, the power balls 182, and the I/O balls 183 to be coupled respectively to the PCB""s VCC (system power), VSS (ground line) and I/O (signal input/output) lines.
Conventionally, the foregoing power/ground ring layout scheme on BGA package can be implemented in many various ways.
FIG. 2 is a schematic diagram showing a conventional power/ground ring layout scheme oh BGA package, which is disclosed in U.S. Pat. No. 5,686,699 entitled xe2x80x9cSEMICONDUCTOR BOARD PROVIDING HIGH SIGNAL PIN UTILIZATIONxe2x80x9d.
As shown, this power/ground ring layout scheme includes the layout of a ground ring 110xe2x80x2 and a power ring 120xe2x80x2 surrounding the packaged chip 160xe2x80x2, which are both shaped in straight lines and directly connected to ground vias 141xe2x80x2 and power vias 142xe2x80x2. Further, a plurality of ground wires 171xe2x80x2 are connected from the chip""s ground pads 161xe2x80x2 to the ground ring 110xe2x80x2, while a plurality of power wires 172xe2x80x2 are connected from the chip""s power pads 162xe2x80x2 to the power ring 120xe2x80x2.
One drawback to the forgoing power/ground ring layout scheme, however, is that since those points on the ground ring 110xe2x80x2 and the power ring 120xe2x80x2 that are already connected to the ground vias 141xe2x80x2 and the power vias 142xe2x80x2 are unbondable areas for the power/ground wires 171xe2x80x2, 172xe2x80x2, it would reduce the routability of the power/ground wires 171xe2x80x2, 172xe2x80x2. Therefore, the layout design for the power/ground wires 171xe2x80x2, 172xe2x80x2 would be difficult.
FIG. 3 shows a solution to the above-mentioned routability problem. As shown, this power/ground ring layout scheme includes the layout of a ground ring 110xe2x80x3 and a power ring 120xe2x80x3 surrounding the packaged chip 160xe2x80x3, wherein the ground ring 110xe2x80x3 is formed with a line portion 111xe2x80x3 and a plurality of branched portions 112xe2x80x3 extending out from the line portion 111xe2x80x3 for connection to ground vias 141xe2x80x3; and in a similar manner, the power ring 120xe2x80x3 is formed with a line portion 121xe2x80x3 and a plurality of branched portions 122xe2x80x3 extending out from the line portion 111xe2x80x3 for connection to power vias 142xe2x80x3. This power/ground ring layout scheme allows the power/ground vias 141xe2x80x3, 142xe2x80x3 to be located beyond the line portions 111xe2x80x3, 121xe2x80x3 of the ground ring 110xe2x80x3 and the power ring 120xe2x80x3, thereby allowing power/ground wires 171xe2x80x3, 172xe2x80x3 to be straight routed to the nearest points on the line portions 111xe2x80x3, 121xe2x80x3 of the ground ring 110xe2x80x3 and the powder ring 120xe2x80x3. Therefore, the power/ground ring layout scheme shown in FIG. 3 has a better routability than the prior art of FIG. 2, allowing the layout design work to be more convenient to implement.
The foregoing solution of FIG. 3, however, Us two drawbacks. First, since the provision of the branched portions 112xe2x80x3, 122xe2x80x3 of the ground ring 110xe2x80x3 and the power ring 120xe2x80x3 increases the length of the power/ground conductive path, it would undesirably degrade the electrical performance of the packaged/chip 160xe2x80x3. Second, it would make the ground ring 110xe2x80x3 and the power ring 120xe2x80x3 farther separated from each other, which would additionally degrade the electrical performance of the packaged chip 160xe2x80x3. Therefore, the power/ground ring layout scheme shown in FIG. 3 would undesirably cause the packaged chip 160xe2x80x3 to have poor electrical performance during operation.
FIG. 4A shows a solution to the foregoing problem of degraded electrical performance, which is disclosed in the U.S. Pat. No. 5,726,860 entitled xe2x80x9cMETHOD AND APPARATUS TO REDUCE CAVITY SIZE AND THE BONDWIRE LENGTH IN THREE TIER PGA PACKAGE BY INTERDIGITATING THE VCC/VSSxe2x80x9d.
As shown, this power/ground ring layout scheme includes the layout of a ground ring 110xe2x80x2xe2x80x3 and a power ring 120xe2x80x2xe2x80x3 surrounding the packaged chip 160xe2x80x2xe2x80x3, wherein the ground ring 110xe2x80x2xe2x80x3 is formed with a line portion 111xe2x80x2xe2x80x3 and a plurality of toothed portions 112xe2x80x2xe2x80x3, and in a similar manner, the power ring 120xe2x80x2xe2x80x3 is formed with a line portion 121xe2x80x2xe2x80x3 and a plurality of toothed portions 122xe2x80x2xe2x80x3. To allow a reduced distance between the ground ring 110xe2x80x2xe2x80x3 and the power ring 120xe2x80x2xe2x80x3, the line portion 111xe2x80x2xe2x80x3 of the ground ring 110xe2x80x2xe2x80x3 is aligned substantially in parallel to the line portion 121xe2x80x2xe2x80x3 of the power ring 120xe2x80x2xe2x80x3, and the toothed portions 112xe2x80x2xe2x80x3 of the ground ring 110xe2x80x2xe2x80x3 are interdigitated with the toothed portions 122xe2x80x2xe2x80x3 of the power ring 120xe2x80x2xe2x80x3.
One drawback to the forgoing power/ground ring layout scheme, however, as illustrated in FIG. 4B, is that those power wires 172xe2x80x2xe2x80x3 that are routed overhead across the line portion 111xe2x80x2xe2x80x3 of the ground ring 110xe2x80x2xe2x80x3 would be easily short-circuited to the ground ring 110xe2x80x2xe2x80x3 due to the sagging of these power wires 172xe2x80x2xe2x80x3 against the line portion 111xe2x80x2xe2x80x3 of the ground ring 110xe2x80x2xe2x80x3.
It is therefore an objective of this invention to provide, a BGA package with interdigitated power/ground ring layout scheme, which can help to increase the routability of power/ground wires.
It is another objective of this invention to provide a BGA package with interdigitated power/ground ring layout scheme, which allows a reduced distance between the power ring and the ground ring for retaining the electrical performance of the packaged chip.
It is still another objective of this invention to provide a BGA package with interdigitated power/ground ring layout scheme, which can prevent power wires from being short-circuited to the ground ring due to sagging against the ground ring.
It is still another objective of this invention to provide a BGA package with interdigitated power/ground ring layout scheme, which can help to increase the efficiency of heat dissipation from the packaged chip.
In accordance with the foregoing and other objectives, the invention proposes an BGA package with an improved power/ground ring layout scheme.
By the invention, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. The power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias. Moreover, solder mask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging. Further, the toothed portions of the power ring and the ground ring are large in area, whereby two or more power vias or ground vias can be gathered together to increase the overall electrical performance, and whereby the packaged chip can be increased in heat-dissipation efficiency.